EEE348 Electronics and Devices
week 1
Trends
The Moore’s Law(1965):“The functionality of devices doubles every 18 months” or “the cost of the same functionality halves every 18 months”
ButIt will come to an end - due to basic physics if nothing else.
The structure of FET(Field Effect Transistor)
Scaling can be done as λ→λ/s (s>1)
| components | rate |
|---|---|
| Area(s^2) | 1/(s^2) |
| Speed(v) | s |
| Capacitance(C) | 1/s |
| Resistance(R) | s |
| RC | 1 |
Intrinsic Limits
The problems might be appeared when reached 10nm fabrication
| Name | Problem | solution | Shortcoming |
|---|---|---|---|
| Gate Oxides | Thinner oxides means increased tunnelling | Change other materials | Have higher εr |
| Gate Electrode Material | Same with the problem in oxides | using metal electrodes | more complex processing |
| Low k Insulators | Lower permittivity are required while device scaled down | perfectelly towards 1 | |
| Lithography | more shorter wavelength required(toward 157nm) | using Extreme UV(13nm soft x-rays used) | light is not powerful enough/expensive |
| Doping | Only 100 dopant atoms in the active region |
History
week2
Implementation technology
There have many possible ways to achieve and implementate a circuit.
Programmed logic devices(PLD):
PLD is the simplest ASIC structure.
The signals inputed from pin 1,2,3 and outputed through pin 17,18,19.
each intersections will be connected by a transistor and a switch, and controlled signals to OLMC.
Complex PLDs (CPLD):
very same to PLD but with higher gate number.
It shared some interconnect logics globally, have fast transmit speed in single macrocell but not between two cells.
Field Programmable Gate Array (FPGA):
FPGA is created by many configurable logic blocks(CLB). Each CLB is progeammable and can implement big range of functions. FPGA can designed by HDL, and access multiple erasing and writing process.
Masked Gate Array (MGA):
Its ICs are manufactured to your specification in a Semiconductor Fabrication Facility (Fab). all og logics are acieved by NAND gate.
Structured ASICs(SA):
Like a combination of FPGAs and MGA. it may have predefined RAM blocks, and other functional units already manufactured into the device
Cell-Based ASICs (or Semi-Custom):
more complex than MGAs in that the design can be composed not just of NAND gates but of gates drawn from a library of cells like NOT,AND,FF,ADD etc.
| name | gate number | delay | cost |
|---|---|---|---|
| PLD | 100 | 1-10ns | $1-2 |
| CPLD | 5000 | 5ns | $10-50 |
| FPGA | 5000-5M | 3-4ns | $50-3000 |
Design flows
Customer: Requirements Specification->Design Specification-> Architectural Soecification->coding in HDL->Synthesis->Placement->Routing->Design Rule
week3
MOS device
MOSFET is combined with Metal-Oxide-Semiconductor(MOS) and Field-Effect Transistors(FET) these two devices. It can differentiated as p-MOSFET and n-MOSFET based on differente using materials.
The n-MOSFET’s cross-section representation is as follows:
| Vbb | Vds | Vgs | state |
|---|---|---|---|
| 0V | 0V | 0V | two back-to-back diodes |
| 0V | 0<Vds | 0<Vgs<Vt | cut-off |
| 0V | 0<Vds | 0<Vt<Vgs | ohmic contact |
| 0V | Vgs-Vt | 0<Vgs<Vt | saturated(pinches-off) |
The current through source and drain can be explaied as:
where λ is Channel-length modulation parameter,
Kn is the value of term
For p-MOSFET bahaves identically to n-MOSFET but with reversed polarities. performed as:
But normally, less current will through p-MOSFET than the n-MOSFET with same area and environment.
CMOS circuit
A CMOS circuit contains both the p-MOSFET and n-MOSFET. But generally less components will contained in reality than imagination.
In digital circuit, the substrate connection for n-MOSFET would be connect to negative supply and p-MOSFET is in reverse.
Inverter Characteristics
The simpliest CMOS circuit is worked as an inverter:
when Vin=0, Vout=1;
when Vin=1, Vout=0;
Threshold value
if we assume Vtp=-Vtn, Kp=Kn, than
Vin=Vdd/2
hence the threshold value can be seen as:
normally, if let Vdd=3.3V, Vt=0.7V, the threshold voltage will changed rapidly.
Parasitics
Many paracitics components have associated in MOSFET
The capacitor can calculated as
Body effect
Normally the stack MOSFETs have same well and share the same substrate voltage,
But in reality Vbb between them will be changed and Vt increases up on the stack.
rise/fall time
week4
The standard CMOS circuit
pull-up network→pMOSFET, pull-down netweork→nMOSFET
figure 2 implements an AND and figure 3 shows OR funvtion.
example:
for nand ligic gate,
Y=A’+B’, Y’=A*B
For XOR gate,
resistance and capacitance calculation
CG: capacitance value on the gate
CD: capacitance value on the drain
A=m1CG+m3CG+m6CG+m8CG
Z=m5CD+m7CD+m8CD+m9CD+m11CG+m12CG
| PULL-down | PULL-up | |
|---|---|---|
| X | R0/m3+R0/m4 | 2R0/m1 or 2R0/m2 |
| Y’ | R0/m8+R0/m10 | 2R0/m5 or 2R0/m6+2R0/m7 |
value of pull-down and pull-up need to be same, assume µE/µH=2, get
m1=m2=2, m3=m4=2
m8=m10=2, m5=2, m6=m7=4.
hence A=10CG, Z=10CD+3CG
pass transistors
using transistor as a switch to open and cloce a circuit.
the output resistance can be R0=5/(β N (VDD −VT ))
transmission gate
R0=1/(β (VDD −VT ))
| A | G | Y |
|---|---|---|
| 0 | 0 | U |
| 0 | 1 | 0 |
| 1 | 0 | U |
| 1 | 1 | 1 |
| U: unknowed, Y’s state can be decided if both n and p MOSFET are closed |
In this case output will never be worried. if G=0, Y=A; if G=1.Y=B.
Week 5
Flip-Flop and latch block diagram
implementation of ltach
but if G changed later than inverser, clock diagram will be in mess, hence clock generation is needed for generate some “delay” area
metastability
problem will happened if D is changing while clk is raising as well. its state will became metastability and influce further functions.
this issue only happenes on asynchronous system
the property of probability is
where tr is the time from clk edge to the time that must output something
tc is constant associated, basically 1/GBW of the sampling circuit
T0 is constant vlaue, is related to technology and circuit design
(the T0 and tc should be small for a good design)
and the number of upsets will be
if upset=288, means every 1/288=3.4ms will cause a problem
in poisson distribution form, the rate of happening k times error in λ seconds is
λ is rT_MTTF(mean time to fail)
where 1-η=P(k;λ)
or
Week6
a n-channel MOSFET
A: VGS=VDS=0
B: Vgs=0, VDS>0
C: VGS>0, VDS<VOV (VOV=VGS-VTo=over drain voltage)
D: VGS>0, VDS=VOV
E: VGS>0, VDS>VOV
week 7
small signal model
for transconductance
Π diagram
T diagram
Week 8
Common source amplifier
a common amplifier to increase output voltage value based on a FET
the input Vg=Vsig+Vbias with relationship like follows:
the red slop have function ID=(VDD-Vd)/RD, and the x/y-axis when it cross the blue curve is seperataly the voltage output from Vout and current through transistor. the cross point need be choicen as in the saturated region and be in middle part as Vbias=2V
gain of this common source amplifier is
common drain amplifier
Vbias=VS(best bias point)+Vov+Vto
for creayting small cignal circuit:
short-circuit any DC voltage source (also change power supply into groung)
short-circuit ant capacitors in circuit
open-circuit any constant current cource of inductors
replace NMOS with equivalent circuit
this amplifer acts like a voltage buffer, accurancy volatge is depends on Q-point.
common gate amplifier
Vs=IdRsig
Av=vd/vsig=gmRd/(gm*Rsig+1)
have low input impedance, non inverting current, unit current gain
voltage gain is same as common source amp
can be used as a current buffer.
| type | volatage gain |
|---|---|
| common source | -RD*gm/r0 |
| common drain | gmRs/(1+gmRS) |
| common gain | gmRd/(gmRsig+1) |
Week9
voltage divider biasing
this circuit can provide high bias stability
but the current flow through M1 will be influenced by temperature with constant VGS supply
by adding a feedback resistor RS can provide a slop in Id diagram, for decreasing this temperature error
but this design still need large number of transistors and large Rs requires more voltage headroom to operate
current source biasing
the current source have provided a stable and constant current flow id, because the voltage error in same current is smaller than the current error produced in same voltage.
but this error can still be decreased if set a FET in the source port to plot the horizontal line
Week 10
current mirror
current through M2 is basically same with current through M1
Iout/Imaster=(W(M2)/L(M2))/(W(M1)/L(M1))
means a constant current biasing is worked
current steering
diode connected
FET works like a diode at this time. the transistor will always in saturated region
hence the voltage and current in M2 can both been controlled based on diode connected.
dy/dx=1/r0=lamuda*Id0
because smaller slope is needed for smaller error, ro need be increased
Wilson current mirror(advanced design)
Vout↓,Im3↓,Im2↓,VGSm2↑,VGSm1↑,IR↓,V1↑,Im3↑
Active loading
load a resistor on drain part
but it can not easily increasing voltage gain course FET will into triode region
can be solved by a FET
Semiconductor
formular sheet: online formular sheet
Week13
Bolck from left to right is Metal, Semiconductor, and Insulator
| Metal | Semiconductor | Insulator |
|---|---|---|
| Conduction band and valence band overlapped | Band gap changed from meV to 9 eV | Band gap larger than 9eV |
| Electrons move freely | no electrons in CB at T=0, get thermal energy kT=26meV wen T=300 | Negligible electron in CB |
| good conductor | depend on number of electrons | no current conduction |
The current density is influenced by both drift and diffusion seperatly with two parts:
where q=1.6*10^-19 as a constant
Electron consentration:
Nc: effective density of state in conduction band
EC: bottom of conduction band
Ef: fermi level
chemical elements table and lattice constant:
more ↓ elements are, more smaller bandgap will have, much bigger the lattice constant is, higher electron mobility
Direct band gap semiconductors (GaAs, InGaAs) are much more efficient emitter than indirect band gap semiconductors (Si,Ge)
Semiconductors with the same lattice constant as the substrate can be grown with minimal crystal defects
week14
Energy level on each electrons is not same with different orbital
and energy level will slightly decrease if more atoms are placed side by it.
If E0, or band gap(the difference between 4th and 5th band) is minimum (then Eg), the semiconductor has a direct bandgap
If Eg is minimum (with E0), semiconductor has an indirect bandgap.
Adachi p.135
importance of carrier mobility: High mobility increases carrier drift velocity.
Carrier velocity ν = μE (μ = mobility, E = electric field)
m is effective mass
Density of states N(E) is defined as the density of allowed energy states per energy range per unit volume.
Schrodinger equation:K+U=E,
where the total energy is given by the sum of kinetic(K) energy and potential(U) energy
some mixed elements, like AlGaAs, its gap energy will change depends on different ratio the different elemrnts it has.
like, Al0.5Ga0.5As has the middle energy between AlAs and GaAs.
AlxGa1-xAs means it has x% AlAs and (1-x)% GaAs.
(the emitted energy is E(eV)=hc/λ(um), h=6.62607015×10^（-34） J·s,c=3*10^(8))
Week 15
Carrier concentration plays a critical role in determining how much current a semiconductor can conduct
Ef is Fermi level corresponding to the probability of electron occupancy of 0.5 in n type semiconductor:
Ec is conduction band, n is electron concentration, Nc is effictive density of states in conduction band, in room temperature kT=26meV
the fermi level in n-type is dependent on the electron concentration
the interinsic carrier concentration ni^2=np
Doping type depends on number of groups in elements table.
N-type: in group V and VI
P-type: in group II and III
Increasing the n-type dopants will increase the conductivity ( hence reduce the resistivity) of the n-type semiconductor.
Carrier Recombination
A: Generation-recombnation due to trap levels(SRH)
B: Rafiative Recombination
C: Auger Recombination
Week 16
The intensity of light travelling through a semiconductor is given by
x is position, alpha is the optical absorption coefficient
multiple materials can be used for maximum absorbe different wavelength.
the wave length will reduced from top to bottom, and bandgap need also reduce to absorb them
dark current is the emitter that without absorbing any photon (band gap energy can only influence dark current)
photo current is the normal light current
the total current when the diode is illuminated (different function in formular sheet?????)
Is=short circuit current
Vov=open circuit voltage
Pm=ImVm=maximm output power
several ways to maximum fill factor: increase Im and Vm:
1.Minimise reflected light at the air/semiconductor interface since ~31% of light is reflected.
2.Maximise light absorption using a thick absorption region.
3.Reduce carrier recombination near the surface which has high density of dangling bonds.
4.Maximise generated photocurrent using materials with long minority carrier diffusion lengths
5.Minimise the dark current using low defect materials. (large bandgap and low temperature also help)
//
Iph measured photocurrent
Popt incident optical power
η quantum efficiency
G(x) optical generation rate
W depletion width
φ0 photon flux
α absorption coefficient
Rres Responsivity
Iph shot noise to
derive the minimum optical power
required to produce SNR =1
x diffuse distance
vs drift velocity
tr transit time
fRC RC time limited bandwidth
A area
τ Recombination lifetime
tr Transit time
σ conductivity of the semiconductor
h Planck constant
p carrier momentum
En quantised energy level
β hole ionisation coefficients
α electron ionisation coefficients
x carrier injection position
F noise factor