介绍

可用STM32模拟鼠标数据控制。

一些基本的Hexo命令行语句。每次修改完记得按流程测试

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$ hexo clean // 清除缓存

$ hexo g // 从新生成html静态文件

$ hexo s // 本地创建 localhost:4000

$ hexo d // 上传域名

Week1

Law

contents of law in this semester are contain with 4 topics:
contract law
Intellectual property (IP) law 知识产权法
Law of Torts 民事侵权法
Environmental law

Contract law

Common law:
The strength of an authority(威权) will depend upon it having like facts to the case in hand and generally that it was decided in a higher court.
The question of what amounts to ‘like facts’ is not always easy
Two very able advocates(提倡者) trying to persuade the court that the strength of authority supports their case rather than the opposition
Have no standard terms and conditions!!!

Contract law regards with civil(民法) law instead of criminal(刑法) law
criminal law: face to social security, operate by state, paid to state and must show defendant(被告) is guilty.
civil law: brought individual who fells have suffered, paid to party who bringing action and claimant(索赔人) must show defendant is liable ‘on the balance of probabilities’(the probability whether defendant is guilty based on evidence from two parties)

contract law regards private not public law
public sector(公共部门) follows public functions is public law, but they purchas pens or paying construction regards private law.

Generally, only the parties to the contract can enforce it in court

Common law and equity are two methods for the judge. common law means sertainty but equity means court can deal the case with discretionary(自由裁量权)

contract is an agreement giving rise to obligations which are enforced or recognised by law.

Why enter into a contract?
• Facilitate exchange/make bargains
• Plan commercial relationship
• Provide certainty
promises are made to be kept; contracts are made to be performed.
voluntarily(自愿的)

Normal method of remedy(解决方法) is awarding of damages. courts try to calculate the case that both parties follow contract and position they would be. sometime it will lead to ‘specific performance’, like enforce them continully follow the contract.

following components have valid contract:
offer
acceptance
consideration
intention to create legal relations
certainty

Week2

offer

Offer is an unequivocal indication of a willingness to be legally bound by a promise if the terms of the offer are met.
like said “100 pounds for each mouse and they will be delivered due to 25th Nov”.
but keep mind that price list and most advertisement are not offer. courts will evaluate if contents in an offer is detailed enough as a contract.

An offer may terminated at any point up until acceptance
An offer will lapse(失效) after a ‘reasonable’ time
An offer will lapse on the failure of a condition precedent
An offer will lapse on the death of the offerer (perhaps)

acceptance

an acceptance means absolute and unequivocal(明确的), and must be communicated (but not postal rule).
if have any attempt to vary term, a counter offer will kill the original offer

consideration

check any anlysis whether is a good bargain or not

but deed(契约) is differente than normal consideration. it may enforceable as what is known as a speciality contract.

intention to create legal relations

assessed objectively and rebuttable presumptions

certainty

Only certain types of contract are required to be in writing (e.g. land) but the more significant a contract the more sense there is in putting it in writing

contract obtains express terms and implied terms. courts may retrospectively( 回顾性地) imply terms into a contract.

the excluding or limiting liability can be included via parties reflects voluntary natureof freedom of contract.

How a contract can be discharged:
• Performance of contract
• By agreement of contractual parties
• Breach of contract
• Frustration of contract
• Contract is voidable due to conduct of a contracting party

Week 3

Discharge a contract:
•compelete the contract
•mutual agreement of contract perties
•breach of contract
•frustration(受挫) of contract
•improper conduct(不当行为)

breach of contract:
repudiatory breach, anticipatory breach

type of damges for breach contract:
punitive/exemplary damages
restitutory damages
compensatory damages: like cost of replacement performance, lost profits, damage to property, persinal injury, damages payable to customer, damage to commercial reputation, emotion distress, loss of pleasure

improperly conduct:
Where one party has acted improperly, the court may deem the contract ‘voidable’ (innocent party can choose to terminate)
1.Misrepresentation
2.Duress(胁迫) & Economic Duress
3.Undue Influence

Week 4

Intellectual Property

type of IP: information, creative expression and design, reputation(声誉), invention

remedies for infringement:
search order
injunctions(警告)
damages
account of profits
delivery up
destruction of the infringing items
limited criminal sanctions

Confidential Information

three requirements for legal protection

1. Information must possess the necessary quality of confidence
2. Information must have been imparted in circumstances imposing obligation(义务) of confidentiality
3. An unauthorised use of that information

Defences to alleged breach of confidence
• Claimant gave consent for info to be disclosed
• Information already in public domain
• In the public interest for info to be disclosed

copyright

!!!Seeks to protect the tangible expression of an idea NOT the idea itself
Life plus 70 years

the copyright automatically vests to author of the work.
requirements:
• The work is original
• The work is recorded in a material form (i.e. protects expression not idea)
• A ‘substantial part’ of work is reproduced without permission
• Author or work is connected to a signatory state of Berne Convention
but author can transfer ownership of copyright

only copyright owner have right to copy, issue copies to public, perform, show, incude and adapt works.

primary infringement: restricyed acts
secondary infringement: Must show knew/had reason to believe items were infringing copies

defences to breach of copyright:
• Deny claimant is owner (or licensee) of copyright work
• Deny work is entitled to copyright protection
• Deny any infringing conduct has been committed

Week 5

trademark: a mark or device usually attached to goods or services which indicates a connection between those goods or services and the trade mark owner.

eample of trade marks: brand name, symbols, shapes, slogans, sounds, colours, celebrity’s image
those mark or device usually attached to goods or services which indicates a connection between those goods or services and the trade mark owner. a trade mark is regisered for a period of 10 years. is a trademark havn’t used for 5 years, it can be revoked.

a trade mark need determine the clear and precise subject matter to which peotection is afforded.
Absolute grounds for refusal: devoid of distinctive character, purely descriptive, estalished practice.
Relative grounds for refusal: if mark conflicts with an earlier trademark.

trade mark is protected by TMA.

Passing off: unregistered trademark

1. protectable reputation.goodwill: must show business has protectable goodwill
2. misrepresentation: miust show that infringing activity took place in the course of trade and the customers were being misled
3. damage to goodwill: need show there have potential demage

Week 6

Patents(专利) is an exclusive right granted for an invention, which is a product or a process that provides, in general, a new way of
doing something, or offers a new technical solution to a problem
Patents can not freely used for 20 years

how to get a patent:
In European Patent Office(EPO), in several EPC members
In PCT, round the world
In UK patent Office, just in UK

The court must use a reference point in determining whether:
• There is an appropriate level of detail in a patent application
• The invention for which the application is made is indeed ‘a step forward’ in terms of development

can not be an invention:
discory, theory or marhematic method, artistic work, mantal act, game, or something is contrary to public policy or morality.

a patent only be granted id the invention is new, has inventive step, and is capable of industrial applicaiton

Financial

accets=non_current assets+current assets
资产=非流动资产+流动资产

equity=assets-liability
股本=资产-负债

Return on capital employed: Operating profit /(Equity + Non-Current Liabilities)
使用资本收益率:营业利润/(权益+非流动负债)
↑

Gross profit margin: Gross profit/Revenue
毛利率:毛利润/收入
↑

Operating profit margin: Operating profit/Revenue
营业利润率:营业利润/收入
↑

Asset turnover: Revenue /(Equity + non-current liabilities)
资产周转率:收入/(权益+非流动负债)
↑, means high current ratio

Inventory days: Closing Inventory x 365 days/Cost of sales
存货周转天数:期末存货x 365天/销售成本
→

Trade receivable days: Closing Trade receivables x 365 days/Revenue
应收账款周转天数:收账应收账款× 365天/收入

Trade payable days： Closing Trade payables x 365 days/Cost of sales
应付账款周转天数:收账应付账款× 365天/销售成本

Current ratio Current Assets/Current Liabilities
流动比率:流动资产/流动负债
↑: can replay the loan

Quick ratio: (Current Assets – Inventory )/Current Liabilities
速动比率:(流动资产-存货)/流动负债
↑: can replay loan swiftly

Gearing: Debt/Equity
杠杆比例:债务/股本
↓

Interest cover: Operating profit/Finance cost
利息:营业利润/财务成本

Dividend cover: Profit for the year/Dividend
利润股息比率:本年利润/股息

keep mind on profitability, liquidity and gearing.

prime cost: direct material or labour ect.
product cost: indirect costs+prime cost
period cost: other supporter cost like office, marketing ect.
total cost= product cost + period cost

Break-even point (BEP) =Fixed costs/Contribution per unit
盈亏平衡点（BEP）=固定成本/每单位的贡献

Margin of Safety=planed sales-Break-even point
安全边际=计划销售额-收支平衡点

week1

complex value

f(z)=f(x+iy)=u(x,y)+iv(x,y)
Re(f)=x=u(x,y)
Im(f)=y=v(x,y)

harmonic function:

By definition a function is called harmonic if it is at least twice differentiable and it satisfies the well-known Laplace equation.

Euler’s formular:

cause

week 2

complex differentiation

A complex function f(x) is differentiable at a point z if and only if the limiting ratio quotient exists.

Cauchy-Riemann equation:

a way to defferentiate a complex funtion

where u=real part and v=imagin part, and a function has a complex derivative f’(z) if and only if its real and imaginary parts are continuosly differentiable and satisfy the Cauchy-Riemann equation:

which is called the conjugate.

also, Cauchy-Riemann equation can find harmonic function as:

analytical functions

A complex function f(z) is called analytic at a point z0 if it has a power series expansion

we can use ratio test to find wheter a complex series is convergent or not by finding the limitation value of n-th term

if L<1, convergent series
if L>1, divergent series
if L=1, the test is inconclusion.

for complex power series, the sequence Cn converges with a limit L. If L=0, the power series converges for all z. If L not equal 0, then

There are four and only four possible types of singularities of a complex function:

1. pole of order n. f(z)=(3z-2)/[(z-1)^2(z+1)(z-4)] has a pole of order 3 at z=1 and simple poles at z=-1 and 4
2. branch points.f(z) = (z − 3)^1/2 has a algebraic branch point at z = 3 and f(z) = ln(z^2 + z − 2)has logarithmic branch points where z^2 + z − 2 = 0
3. Essential singularity. the singularity is not pole or branch point.
4. singularities at infinity

Taylor’s theorem

If a=0, the series can called Maclaurin series.

Week3

for the series have negative powers of (z-z0), equations can be writen like

Laurent’s theorem

Let function f(z) be analytical in annulus R<|z-z0|<ρ, it can be writen as

Where R belongs to negative part and ρ belongs to positive part.

really conplex content, remember to work the tutorial out.

week 4

three most common form to write a complex function:
ax+by=c,
where a,b are real numbers and x,y are variables
|z-1|=|z-b|
where a,b are complex numbers
z=at+b
where t is real and a,b are complex quantities

euqation can be
(x-x0)^2+(y-y0)^2=R^2,
|z-z0|=R, z0=x0+iy0

z=x+iy=(x0+Rcosφ)+i(y0+Rsinφ)=z0+Re^iφ (0<=φ<2Pi)

integration and Cauchy’s theorem

Newton-Leibnitz formula

the equation C: z=z(t), a<=t<=b,

example:

using linear integration

if f(z)=u+iv=2+i, z=x+iy, than x=2t, y=t.

Week5

Cauchy’s theorem

for two points x1=a1+ia2, x2=b1+ib2,
z=(1-t)(a1+ia2)+t(b1+ib2) (0<t<1)
or for circuit center z0=z1+iz2, radius=R,
z=z1+iz2+R(e^iφ) (0<φ<2Pi)

to Taylor series:

Week6

Residue Theorem

Let z=z0 be a singularity of the function f(z), the coefficient a is called residue of the function f(z)

the single residue (with single power) can be calculated as

but in multiple power, the function can be changed as

for closed contour C be the boundary of domain D,

for calculating real integrals, the contour C can be drawn as

which have ignored all results with negative imaginary.

where first interial is total contour results, second one is the real integrals and third one is the curve covered this domain(most cases equals to 0)

Week7

vector calculus

scalar field: f=x+y+z
vector field: u=(p,q,r)

for scalar field f, its gradient can be written as

the functions of div and curl operators are

grad(f)=∇(f)
div(f)=∇.f
curl(f)=∇*f

like the function curl(div(u)) can not be defined cause div(u) is a scalar which can be curl which.

and there have two conditions the result will be 0:

1. for any scalar f, curl(grad(f))=0
2. for any vector u, div(curl(u))=0

for function div(grad(f))=∇.(∇(f))=fxx+fyy+fzz=∇^2(f), or called Laplancian (scalar field)
and curl(grad(f))=curl(fx,fy)=fyx-fxy=0

Week 8

a vector field u will have a potential function p (which is ∇(p)=u), only when u is conservative:
∇*u=0

if E=(2x+xy,2y+xz,2z+xy)

Week 9

Integration along curve

a curve r=(x(t),y(t),z(t)) in the range of t(a<=t<=b),

where F=∇(p)

if F is a conservative vector fild, the potential function p for F is

value if a,b,c is not stable and can be choicen what ever we want. it is only valid for conservative field

if we want calculate its perdicular vector n then dt, get

Week 10

Surface Integrals

two-dimansional divergence theorem

D is region in plane which boundary is cloased curve C. dA=rdrdtheta
if D is surrounding with multiple curve C, they need to be added

Green’s theorem

when dA=ndA, n is unit normal vector to D and u=(P,Q),

three-dimansional divergence theorem

almost same with two-dimansional divergence

stokes’ theorem

cause if follows function in two-dimentional theorem, the direction of vertical vector n is cant been decided. hence two choice have in this function

week 1

Trends

The Moore’s Law(1965):“The functionality of devices doubles every 18 months” or “the cost of the same functionality halves every 18 months”
ButIt will come to an end - due to basic physics if nothing else.

The structure of FET(Field Effect Transistor)

Scaling can be done as λ→λ/s (s>1)

Intrinsic Limits

The problems might be appeared when reached 10nm fabrication

History

week2

Implementation technology

There have many possible ways to achieve and implementate a circuit.

Programmed logic devices(PLD):
PLD is the simplest ASIC structure.


The signals inputed from pin 1,2,3 and outputed through pin 17,18,19.
each intersections will be connected by a transistor and a switch, and controlled signals to OLMC.

Complex PLDs (CPLD):
very same to PLD but with higher gate number.
It shared some interconnect logics globally, have fast transmit speed in single macrocell but not between two cells.

Field Programmable Gate Array (FPGA):
FPGA is created by many configurable logic blocks(CLB). Each CLB is progeammable and can implement big range of functions. FPGA can designed by HDL, and access multiple erasing and writing process.

Masked Gate Array (MGA):
Its ICs are manufactured to your specification in a Semiconductor Fabrication Facility (Fab). all og logics are acieved by NAND gate.

Structured ASICs(SA):
Like a combination of FPGAs and MGA. it may have predefined RAM blocks, and other functional units already manufactured into the device

Cell-Based ASICs (or Semi-Custom):
more complex than MGAs in that the design can be composed not just of NAND gates but of gates drawn from a library of cells like NOT,AND,FF,ADD etc.

Design flows

Customer: Requirements Specification->Design Specification-> Architectural Soecification->coding in HDL->Synthesis->Placement->Routing->Design Rule

week3

MOS device

MOSFET is combined with Metal-Oxide-Semiconductor(MOS) and Field-Effect Transistors(FET) these two devices. It can differentiated as p-MOSFET and n-MOSFET based on differente using materials.

The n-MOSFET’s cross-section representation is as follows:

The current through source and drain can be explaied as:

where λ is Channel-length modulation parameter,
Kn is the value of term

For p-MOSFET bahaves identically to n-MOSFET but with reversed polarities. performed as:

But normally, less current will through p-MOSFET than the n-MOSFET with same area and environment.

CMOS circuit

A CMOS circuit contains both the p-MOSFET and n-MOSFET. But generally less components will contained in reality than imagination.
In digital circuit, the substrate connection for n-MOSFET would be connect to negative supply and p-MOSFET is in reverse.

Inverter Characteristics

The simpliest CMOS circuit is worked as an inverter:


when Vin=0, Vout=1;
when Vin=1, Vout=0;

Threshold value

if we assume Vtp=-Vtn, Kp=Kn, than
Vin=Vdd/2
hence the threshold value can be seen as:

normally, if let Vdd=3.3V, Vt=0.7V, the threshold voltage will changed rapidly.

Parasitics

Many paracitics components have associated in MOSFET

The capacitor can calculated as

Body effect

Normally the stack MOSFETs have same well and share the same substrate voltage,

But in reality Vbb between them will be changed and Vt increases up on the stack.

rise/fall time

week4

The standard CMOS circuit

pull-up network→pMOSFET, pull-down netweork→nMOSFET

figure 2 implements an AND and figure 3 shows OR funvtion.

example:
for nand ligic gate,
Y=A’+B’, Y’=A*B

For XOR gate,

resistance and capacitance calculation

CG: capacitance value on the gate
CD: capacitance value on the drain

A=m1CG+m3CG+m6CG+m8CG
Z=m5CD+m7CD+m8CD+m9CD+m11CG+m12CG

value of pull-down and pull-up need to be same, assume µE/µH=2, get
m1=m2=2, m3=m4=2
m8=m10=2, m5=2, m6=m7=4.

hence A=10CG, Z=10CD+3CG

pass transistors

using transistor as a switch to open and cloce a circuit.

the output resistance can be R0=5/(β N (VDD −VT ))

transmission gate

R0=1/(β (VDD −VT ))

In this case output will never be worried. if G=0, Y=A; if G=1.Y=B.

Week 5

Flip-Flop and latch block diagram

implementation of ltach

but if G changed later than inverser, clock diagram will be in mess, hence clock generation is needed for generate some “delay” area

metastability

problem will happened if D is changing while clk is raising as well. its state will became metastability and influce further functions.
this issue only happenes on asynchronous system

the property of probability is

where tr is the time from clk edge to the time that must output something
tc is constant associated, basically 1/GBW of the sampling circuit
T0 is constant vlaue, is related to technology and circuit design
(the T0 and tc should be small for a good design)

and the number of upsets will be

if upset=288, means every 1/288=3.4ms will cause a problem

in poisson distribution form, the rate of happening k times error in λ seconds is

λ is rT_MTTF(mean time to fail)

where 1-η=P(k;λ)

or

Week6

a n-channel MOSFET

A: VGS=VDS=0
B: Vgs=0, VDS>0
C: VGS>0, VDS<VOV (VOV=VGS-VTo=over drain voltage)
D: VGS>0, VDS=VOV
E: VGS>0, VDS>VOV

week 7

small signal model

for transconductance

Π diagram

T diagram

Week 8

Common source amplifier

a common amplifier to increase output voltage value based on a FET

the input Vg=Vsig+Vbias with relationship like follows:

the red slop have function ID=(VDD-Vd)/RD, and the x/y-axis when it cross the blue curve is seperataly the voltage output from Vout and current through transistor. the cross point need be choicen as in the saturated region and be in middle part as Vbias=2V

gain of this common source amplifier is

common drain amplifier

Vbias=VS(best bias point)+Vov+Vto

for creayting small cignal circuit:
short-circuit any DC voltage source (also change power supply into groung)
short-circuit ant capacitors in circuit
open-circuit any constant current cource of inductors
replace NMOS with equivalent circuit

this amplifer acts like a voltage buffer, accurancy volatge is depends on Q-point.

common gate amplifier

Vs=IdRsig
Av=vd/vsig=gmRd/(gm*Rsig+1)

have low input impedance, non inverting current, unit current gain
voltage gain is same as common source amp
can be used as a current buffer.

Week9

voltage divider biasing

this circuit can provide high bias stability

but the current flow through M1 will be influenced by temperature with constant VGS supply

by adding a feedback resistor RS can provide a slop in Id diagram, for decreasing this temperature error


but this design still need large number of transistors and large Rs requires more voltage headroom to operate

current source biasing

the current source have provided a stable and constant current flow id, because the voltage error in same current is smaller than the current error produced in same voltage.

but this error can still be decreased if set a FET in the source port to plot the horizontal line

Week 10

current mirror

current through M2 is basically same with current through M1
Iout/Imaster=(W(M2)/L(M2))/(W(M1)/L(M1))
means a constant current biasing is worked

current steering

diode connected

FET works like a diode at this time. the transistor will always in saturated region

hence the voltage and current in M2 can both been controlled based on diode connected.

dy/dx=1/r0=lamuda*Id0
because smaller slope is needed for smaller error, ro need be increased

Wilson current mirror(advanced design)

Vout↓,Im3↓,Im2↓,VGSm2↑,VGSm1↑,IR↓,V1↑,Im3↑

Active loading

load a resistor on drain part

but it can not easily increasing voltage gain course FET will into triode region

can be solved by a FET

Semiconductor

Adachi: https://find.shef.ac.uk/primo-explore/fulldisplay?docid=44SFD_ALMA_DS51248442680001441&context=L&vid=44SFD_VU2&lang=en_US&search_scope=SCOP_EVERYTHING&adaptor=Local%20Search%20Engine&tab=everything&query=any,contains,adachi&offset=0

formular sheet: online formular sheet

Week13

Bolck from left to right is Metal, Semiconductor, and Insulator

The current density is influenced by both drift and diffusion seperatly with two parts:

where q=1.6*10^-19 as a constant

Electron consentration:

Nc: effective density of state in conduction band
EC: bottom of conduction band
Ef: fermi level

chemical elements table and lattice constant:


more ↓ elements are, more smaller bandgap will have, much bigger the lattice constant is, higher electron mobility

Direct band gap semiconductors (GaAs, InGaAs) are much more efficient emitter than indirect band gap semiconductors (Si,Ge)

Semiconductors with the same lattice constant as the substrate can be grown with minimal crystal defects

week14

Energy level on each electrons is not same with different orbital

and energy level will slightly decrease if more atoms are placed side by it.

If E0, or band gap(the difference between 4th and 5th band) is minimum (then Eg), the semiconductor has a direct bandgap
If Eg is minimum (with E0), semiconductor has an indirect bandgap.

Adachi p.135

importance of carrier mobility: High mobility increases carrier drift velocity.

Carrier velocity ν = μE (μ = mobility, E = electric field)
m is effective mass

Density of states N(E) is defined as the density of allowed energy states per energy range per unit volume.

Schrodinger equation:K+U=E,
where the total energy is given by the sum of kinetic(K) energy and potential(U) energy

some mixed elements, like AlGaAs, its gap energy will change depends on different ratio the different elemrnts it has.
like, Al0.5Ga0.5As has the middle energy between AlAs and GaAs.
AlxGa1-xAs means it has x% AlAs and (1-x)% GaAs.
(the emitted energy is E(eV)=hc/λ(um), h=6.62607015×10^（-34） J·s,c=3*10^(8))

Week 15

Carrier concentration plays a critical role in determining how much current a semiconductor can conduct

Ef is Fermi level corresponding to the probability of electron occupancy of 0.5 in n type semiconductor:


Ec is conduction band, n is electron concentration, Nc is effictive density of states in conduction band, in room temperature kT=26meV
the fermi level in n-type is dependent on the electron concentration
the interinsic carrier concentration ni^2=np

Doping type depends on number of groups in elements table.
N-type: in group V and VI
P-type: in group II and III

Increasing the n-type dopants will increase the conductivity ( hence reduce the resistivity) of the n-type semiconductor.

Carrier Recombination
A: Generation-recombnation due to trap levels(SRH)
B: Rafiative Recombination
C: Auger Recombination

Week 16

The intensity of light travelling through a semiconductor is given by

x is position, alpha is the optical absorption coefficient

multiple materials can be used for maximum absorbe different wavelength.
the wave length will reduced from top to bottom, and bandgap need also reduce to absorb them

dark current is the emitter that without absorbing any photon (band gap energy can only influence dark current)
photo current is the normal light current
the total current when the diode is illuminated (different function in formular sheet?????)

Is=short circuit current
Vov=open circuit voltage
Pm=ImVm=maximm output power

several ways to maximum fill factor: increase Im and Vm:
1.Minimise reflected light at the air/semiconductor interface since ~31% of light is reflected.
2.Maximise light absorption using a thick absorption region.
3.Reduce carrier recombination near the surface which has high density of dangling bonds.
4.Maximise generated photocurrent using materials with long minority carrier diffusion lengths
5.Minimise the dark current using low defect materials. (large bandgap and low temperature also help)

//
Iph measured photocurrent
Popt incident optical power
η quantum efficiency
G(x) optical generation rate
W depletion width
φ0 photon flux
α absorption coefficient
Rres Responsivity
Iph shot noise to
derive the minimum optical power
required to produce SNR =1
x diffuse distance
vs drift velocity
tr transit time
fRC RC time limited bandwidth
A area
τ Recombination lifetime
tr Transit time
σ conductivity of the semiconductor
h Planck constant
p carrier momentum
En quantised energy level

β hole ionisation coefficients
α electron ionisation coefficients
x carrier injection position
F noise factor

week1

Application Specific Integrated Circuits(ASICS)

ASICs are silicon chips that have been designed for a specific purpose

Full Custom Design

• the highest performance
• the most expensive and time consuming to produce

Semi-Custom Design

for Gate Array:

• predefined on silicon wafer
• need to define the interconnections for final device

for Standard Cell:

• predefined functional blocks improve layout density and performance.

Field Programmable Gate Array (FPGA)

• contain configurable logic resources and memory
• are most useful for prototyping and can be cost effective for low volume production runs.

Software tools enable users to enter designs, simulate them to ensure correct functionality and then synthesize a solution for a chosen target device.

Verilog

Basic structure

The module body describes the functionality of the model and the relationship between the input and output ports.

The keyword wire is used to declare internal signals. For example:

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module Add_full(output c_out, sum, input a, b, c_in);
	wire w1, w2, w3;
	Add_half M1(w2, w1, a, b);
	Add_half M2(w3, sum, c_in, w1);
	or (c_out, w3, w2);
endmodule

User Defined Primitives (UDP)

The module descripted by truth table

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primitive mux_21_udp(output f, input s, a, b);
	table
		// s a b : f 
		0 0 ? : 0 ; //(? means not care)
		0 1 ? : 1 ; 
		1 ? 0 : 0 ;
		1 ? 1 : 1 ;
	endtable
endprimitive

Port mapping

Another writing format can not stricly follow the variables’ order.

When the number of ports grows larger, it is easier to associate ports by their names.

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Add_half M1 (.b(b), .c_out(w2), .a(a), .sum(w1));

Week2

delay module

Propagation delay: time from the input changing to the output responding.

Inertial delay model(for components): changes to the output of ogic gates can not happen instantly due to the charging and discharging of capacitances.(6ps)
If the width of an input pulse is shorter than the inertial delay, the input pulse is supressed and the output will not change in response to it.

Transport delay model(for wire): Time taken for a signal to propagate alonga wire.(1ps)

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Example:
`timescale 10ps / 1ps //<time_unit>/<time_precision>
module timedelay (f, a ,b);
input a, b;
output f;
nand #2.58 (f, a, b);
endmodule

#2.58=2.58*10ps=25.8ps rounded to 26ps

four-value logic system

1 – assertion (True)
0 – de-assertion (False)
x – unknown (ambiguous)
z – high impedance (disconnected from driver)

nets: build connections but not store values, like wire.
registers: store value and informations

Week3

Register file

The registers in a CPU can be grouped into a register file. Two outputs are supplied in order to feed the ALU.

shifter

standard bidirectional shift register: A multiplexer on each input gives a choice of left shift, right shift, parallel load and no-shift, by selecting the source of the D input appropriately.

Combinational Shifter: shift data using multiplexers. B1,2,3 is input and H1,2,3 is output.

Barrel Shifter: The circuit rotates its contents left from 0 to 3 positions depending on S

Arithmetic Logic Unit

the logic circuit (bitslice):

arithmetic unit:

week4

pictorial representation of 4-bit unsigned inteder:

2s-complement representation of 4 bits inteder:

note that h(-5)=b(1011)=-(2)^3+2^1+2^0

fixed-point 2’s-complement numbers

multiplication

hardware multiplication

multiplicand will delay 1 bit after each operation like 0000 1101→0001 1010
multiplier will shift to right after each step like 1011→101.
product will save results output from adder. but changing process will be cancled if the most right side digital number in multipier is “0”.

combinatorial multiplication

2-digit number A=(a10+a0) B=(b10+b0)
AB=(a1b1)00+(a1b0+a0b1)0+(a0*b0)

Booth’s Algorithm

the equation cna be writen as

for example the euqation 43*12 can be explained as

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   43 = 00000101011
* 12 = 00000001100(0)
---------------------------
     0 = 00000000000  //multiplier bits 0(0)
+  0 = 0000000000|0  //multiplier bits 00
- 172=111010101|00  //multiplier bits 10
+  0 = 00000000|000  //multiplier bits 11
+688=0101011|0000  //multiplier bits 01
----------------------------
   516=01000000100

the relationship between multiplier and operation is

Week6

for A%B=C……D,
A is dividend
B is divisor
C is quotient
D is Remainder

for binary division, comparetion is the only thing need to do

and its implementation is

non-restoring/restoring division

restoring division: the dividiend will turn into previous value if result is negative
non-restoring division: don’t restoring the value if result is negative

the sign of operation is inversed with divided’s signal (“-“ if divident is positive and “+” if divident is negative)
if result if negative, ouput 0; if result is positive, output 1.

example: 456/23 by non-restoring division

floating point

the value of point numbrt can be explaination as m*2^e, where m is mantissa and e is exponent

The IEEE-753 floating point number can can be formulated as

with 32 bits and 64 bits these two types

value in exponent will have a bias which bigger (127 in 32 bits and 1023 in 64 bits) than what we expected

example: turn -93.625 into 32 bits

1. 93.625=1011 101.101 in binary
2. it = 1.0111 0110 1 *(2^6)
3. in 32 bits, it have 127 bias. Hence exponent=6+127=133=1000 0101
4. remove this first “1”, get 0.0111 0110 1, hence 0111 0110 1 is fraction
5. it is a negative number, hence sian bit =1.

therefore, get 1|1000 0101|0111 0110 1000 0000 0000 000 (23 bits)

Week 7

Memory resources

normally instructions are stored in main memory as a program and decode them when programe is required.

the address of each lines of programe is counted by a program counter (PC) which can count and load new addresses from status flags.

MIPS processor

MIPS is a Reduced Instructure Set Computer(RISC). it have 32 registers which have 32 bits wide for each, for byte addressing.

A MIPS word is 32 bits or 4 bytes but giving 2^30 memory words.

big endian: the most byte will stored in lowest address.
little endian: than least byte will stored in lowest address.

three ways have been developed based on MIPSformat


MIPS example
op: opening code
rs: register source
rt: register traget
shamt: shift amount (is not applicable when is 0)
immediate: value of offset

I-type: fast way to load a register and dont need extra memory refrence to fetch operand. but only constant can be supplied and is limitied by bit numbers as well.
example: addi $1,$2,20 : $1=$2+20
R-type: small address field required, shorter instructions possible and have a very fast execution. useful foe frequently operations like loop. but the number and space od address have all been limited.
example: add $3, $4, $5 : $3=$4+$5

Intel X86 Architecture

If the sort of instructions are increasing , a BIU can greatly control them.

where EU is for executing instructions,
BIU is for fatching instructions, reading operands and writing results

however, although X86 is a 16 bit controller but have a 20 bits register.

each segment represents a 64k block of memory, which is combined with an offset address in instruction pointer(IP).

Pipeling instruction: the execute and next fetcj have overlapped to reduce the time used on a cycle
Von Neumann Architecture: single interface for both data and instructions. but an instruction fetch and data opeartion can not occure at the same time cause they share a common bus
Harvard Architecture: seperate the interface of data and instructions. the program memory accesses and data accesses can operated paralllel.

Week 8

register control

four single bit X,Y,W,Z can separately control input and output for both two registers.
data from register B will move to register C if w=0,y=1,x=1,z=0

PC,R2: denotes a register
PC(7:0),R2(1),PC(L): denote a range of register
R1←R2, PC(L)←R0: denotes data transfer
R3←M[PC]: specifies a memory address

like R1←R1+R2 add the results to R1 for additoin of R1 and R2
X.K1: R1←R1+R2 if X.K1=1, R1 will be placed the value of R1+R2
(normally, X.K1 will be the enable port in register)

Week9

Stack

the stack is allocated in main memory and operates as a last in first out block of memory

the flow control istructions change the PC constant with three order：
HALT: places the processor in an idle state
JUMP: change the PC content to a pointed address
CALL: like jump but CPU must remember the return point and return after finishing

the LIFO stack with two operations:
PUSH: puts value into stack
POP: Retrieves the last value that was pushed onto the stack
do not operate POP to a empty register or PUSH value in a full register

a stack pointer register (PC) can be used to allocate the final register

cache

cache is a safe place for hiding and storing things

CPU will first view cache when want read the memory. if it find the memory in cache, called cachehit, in opposite state, called cache miss and CPU will fins the memory from register and copied it into cache again

Direct Mapped Chache: each block is mapped to a single cache location

it is simple and easy for implementaion but have poor performance

Full Associative Cache: each block is mapped to any cache location

all memory block can be mapped but harder for implementation

Set Associative Cache: each block is mapped to any block in a subset of cache location

the best way

cache mapping

V: a valid bit to indicate if address contains valid data
TAG: determines which block of memory is in cache
INDEX: select block in cache
OFFSET: select a byte number got multiple byte blockes

for direct mapped cache: memory=TAG+INDEX
for full sccociative cache: memory=TAG+OFFSET

Week10

Digital filters

for transimiting and receiving analog signals, need to use ADC and DAC

Finite Impulse Response (FIR) Filter
consider a 4-point averaging window and get a stable curve results

the implmentation of builidng blocks are contained with Multiplier, Adder and Unit delay

Algorithmic state machine chart

state box: unconditional, moorly output which only depends on current input values

decision box: conditoinal, mealy output which not only depends on input, but past output results

decision box can have multiple outputs depends on decisions made

conditional box:

an ASM box must consists of a state box, decision box and conditional box
usually start with state box and end before the next state box

implementation

controller logic can obtain condition box and state transition
data procesor can contain operations described in state box and conditoin box

Topic 1

Unit impulse: 𝛿[n]=0 (n≠0), or =1 (n=0)
Unit step: u[n]=0 (n<0), or =1 (n≥0)

for a sinusoid:
𝑥[𝑛]=A cos(𝜔0 𝑛+𝜙)
𝜔0:Normalised frequency
𝜙:Phase delay

Normalised frequency in radians/sample:
𝜔0=Ω0⁄𝑓𝑠,
where Ω0=2𝜋𝑓, is the real angular frequency, fs is sampling frequency

if angular frequency=𝜋 rad/sec, frequency=𝜋/2𝜋=0.5Hz
if a 1 Hz sine sampled by frequency of 10Hz, 1/10=0.1 cycle per sample
angular frequency = 2𝜋*0.1 cycle per sample =0.2𝜋 radians per sample

Important properties of sequences:
Linearity: y[n]=T{x1[n]+x2[n]}=T{x1[n]}+T{x2[n]}
Time invariance: y[n-k]=T{x[n-k]},

Stablility: input and output is bounded
Causality: y[n0]=T{x[n<n0]}

note: Linear and time-invariant = LTI system

Linear constant coefficient difference (LCCD) equation:
LTI systems can be described by a difference equation of the form

impulse response (can be explained by convolution)

where n in figure is a random constant value,
assuming n=-1, f1[k]=[1,2,3], f2[k]=[1,0,1,2]

week1

Si: signal input
Ni: noice input
So: signal output
No: noice output

Noise in AM systems

assuming have noise vlotage/current ni(t) and R=1Ω, the noice power Ni:

ni(t) in terms on in-phase and out-of-phase components in the baseband

can get:

where is the average value of nc(t)^2.

hence

Noise performance of DSB SC using coherent detection

the input ti detectoe and time average input power signal is:

if the demodulator the signal using a perfectly same carrier signal, the signal outputcan be:

as have defined before, the input signal can simply write as the average value of ni^2(t) and no(t)=ni(t)*cos(Wct) and

hence the noise rations is:

Noise performance of DSB LC using envelope detection

r(t) is the output from envelope detector. If ns(t)^2 is much larger than its denominator, hence

By the same calculation, get

Noice in FM signal

The FM receiver can be drawn as

Liliter here is ideal and could removes all amplitude variations.

Input signal si(t) can be written as:

cA: the maximum frequency deviation(same value as ∆ω)
α: signal amplitude
β: the modulation index(β=∆ω/ωm)

and the time average output signal power is:

K: constant associated demodulator system

hence the noice output power is proportional as ω

Pre-emphasis and de-emphasis FM systems

from the figure above, find the noice power density is at its highest when signal strength is at its smallest.
hence pre increase/decrease strength before modulating singal can solve it

Week2

entropy

The entropy, or H, is the average information carried per message of stmbol

like if p(0)=0.2 and p(1)=0.8, H=-(p(0)log2(p(0))+p(1)log2(p(1)))

the relationship between proporty and H is

Huffman coding

for different appear porporty for letter ABCDE, different combination have been used to arrange them.
the bigger proporty a letter has, the less diginal number will used on it.

the average number per message Huffman code will sent can be calculated as
n’=10.74+20.12+30.07+40.06+4*0.01=1.39 bits/message
but if using entropy the value will changed as
H=-(0.74log2(0.74)+0.12log2(0.12)+…+0.01log2(0.01))=1.26 bits/message

the efficiency of Huffman codeing is 1.26/1.39=91%

Strcuture sequences and data compression

Compression is used to reduce the number of bits required to send a piece of information.

Or can usig run-length encoding, which have combain all continous same colors into entire part(like color name + numbers) to reduce store places

But Variable data rate required - the channel bandwidth will be constant, so
buffers are needed.
And A bit error can cause large areas of picture to be incorrect - a low error
rate is needed.

Lossless and lossy coding

run-length coding is an example of lossless coding, cause all bits and data is important in series.
Lossy coding can loss pieces of message and the rest of data can also been used. such as sound and pictures.

week 3

intriduction of digital communications. find the advantages and diaadvantages exsists in digital communications.

Advantages

Channel coding: the process of adding redundant code to a message in order to help the receiver correct any errors which may have occued in transit. (like 0 001 1111, which first 0 is a checking bit without any meaning)

Source coding: Source coding is the process of modifying the way we send the data.

Multiplexing: In transmission systems we often want to make many different signals occupy the available transmission space, this is called multiplexing.

Frequency division multiple access (FDMA): different baseband range will allocated to different user in same time.

Time division multiple acces (TDMA): whole baseband will allocated to user but in part of whole times.

Code division multiple access (CDMA): both time and baseband will be divided and allocated to different users (most effieiency way, and evry secure)

Encryption : data will be coded by a key and decoded by a same key when receive it.

Regeneration: The signal need to repeate transimited signals every regulat times and both signal and noise will strengthed and finally noise will larger than signal in analogue signal. But in channel coding every small noise will be removed while repeat the signals.

Disadvantages

Bandwidth effiency: An analogue transmission system will always occupy less bandwidth than a digital system sending the same message. For some times we can using M-Ary to ease this problem.
Please note: the sample frequency in ADC need larger than 2 times of original signal frequency.

Whats more, digital signals need translate to analogue signals finally, and need synchronisation send and receive environment. It can be more complex to send a digital message.

week4

channel coding

Probability of errors: a binary message sent with bit 0 ir 1 have a probabitity p to turn into wrong bit

Pε = P (0→1)× P (1) + P (1→0) P (0)

random error

Random errors are typically caused by additive white Gaussian noise (AWGN).
Probability density function (PDF) is determined the magnitude for Gaussian in nature

the funtction form of PDF is

which where σ is the standard deviation and a0(1) is the mean of the distribution for logic 0 (1).

hard decisions and soft decisions

hard decision is what figure shows above. is usually sdequate for channels with small amounts of AWGN.
soft decision is return 1 or 0 if a is bigger or smaller than am. is usually for high AWGN noise.

multiple random errors

parity check bits

A single bit parity check code is a simple algebraic code.

convolution coding

a more powerful technical for correction random errors.
for example, initially loaded with 000 and subjected to input data 11011

where u1=D0+D1+D2, u2=D0+D2

the output result will changed in a constant rules hence some small errors will be found out and perhaps been solved.

reed-solomon code

Reed-Solomon codes are in essence parity check codes, although the method by which the additional bits are derived is significantly more complex to enable burst errors corrections.
n: the final length of the code
k: the initial length of the code
t: number of symbol errors can be corrected(2t=n-k)

Week5

Pseudonoise(PN) is a noise but in completely derministic. it can presrve and srcurity signals in channel from other influences.

features for a good pseudomoise sequence

Balance: want roughly same number of 0 and 1
Run sequence: a sequence of consecutive bits with same value. and 1/2 of sequecy should be length of 1, 1/4 be length of 2 and 1/8 be length of 3.
Autocorrelation: have a low correlation with shifted copies with itself.

like 15-bit sequence 100110101111000,
8 of “1” and 7 of “0”, achieved balance
4 of 1 length, 2 of 2 length, 1 of 3 length and 1 0f 4 length, roughlt achieved run sequence.
100110101111000
xor
010011010111100
=
110101111000100
autocorrelation of -1 (sane with other shift situations, fit the autocorrelation)

the good autocorrelation can be used in synchronisation communications cause receiver can easily find the code word by calculating correlation function between its stored PN code and the incoming data stream.

generation PN code

a shift register connected in feedback via a modulo-2 adder can genarate PN code

if n=3, and initial S1=0, S2=1, S3=1, get

repeat 7 times (for n length, the maximum number is =2^n-1, called maximal length sequency)

get output sequency 11100101.

be attention: the initialize code can’t be “000” cause no “1” can be generated through “0”s

non maximal length PN codes

“Gold code” is designed cross-correlation properties are used
and “Barker codes” are sequences which only have 2-valued autocorrelation function. for example

by wrapping the code with itself, get

only 1 and 5 these two values.

Week6

DSSS: direct dequence S.S.
FHSS: frequency hopping S.S.

advantage of S.S. system:
Low probability of interception, interference rejection, higher data rates, and multiple access

DSSS

the message m(t) will first modulated with a PN code which changes much faster than original and much similar with a noise signal.

hence usually this signal is useless unless reveicer have the same PN code to demodulate it.
and definitely, the PN code c(t) in receiver part need to be synchronised with incoming signal to demodulate correctly.

G=Tb/Tch

search mode

the control logic will detectwhether PN code have schieve the synchronisation type by energy. if it is not synchronised, energy during BPF(bandpass filter) will very small and then deley time td will be adjusted. but if in synchronised mode then the energy during BPF region will be strong enough to detect.

check mode

the check mode will compear the signal reveiced between early and late part. the synchronisation will be achieved if these two parts have identical values.

if PN generator is early generated, the shadow area in early part will smaller than late part and VCO will changed the time sequence to adjust it.

noise suppression

the AWGN(additive Gaussian white noise) have finite power over an infinite bandwidth. the de-spearding operation for a ready-spreaded signal can increased power in signal and decrease influence from such white noise.

the jamming signal can be signal with high power and narrow bandwidth. but it can also be decreased after de-spreading.

FHSS

frequency hopping spreads the data signal on one of a series of carriers occupy a really large bandwidth.it is required the bandwidth containing carrier frequency is much larger than data bandwidth. (more than one hoppings in a bandwidth)

final signal will be modulated for two times and its final frequency can be drawed as

final signal frequency=f(carrier)+f(offset)

the processing gain for a frequency hopping system is given as
G=fh*Ts

slow hopping system: the duration of a message bit sorresponds to the inverse hop rate.
fast frequency hopping: would suffer a noise or jamming signal in many parts of the bandwidth.

Week 7

The filter at the receiver end plays a vital role in determining the performance of a communications link.
good filter:

for the required matched filter’s impulse response h(t) can be

Transversal filter

integraie and dump matched filter

this matched filter can only be used for binary signal
with the previous function s(t)=1 and stop in t=T, the correlation figure can be drawn as

and note the shape of dquare wave is distorted by matched filter

the duration of g(t) can roughly implemented as

the switch is open when t<T, till the sample is gotten. the circuit can then determined the capacitor voltage, output it can clean for next sample collection.

and we can also change previous function g(T) and implementation as

matched filter detedtion of PCM codewords

it is quite same with correlation implements before but with PVM code to reject some of noise

the most significant bit will be placed in the last and other bit will be filled with PCM code word
like if want transfer “3” in 8 bits with PCM “1101”, the code will be 00 1101 11 for transfter the important message at first.

Week 8

Essentially, all models are wrong, but some are useful.
George E. P. Box

介绍

IIC协议是一种通用connection method，通过SCL和SDA双线通讯，可以通过设置地址来实现多主机/从机共用双线通讯，节省端口。但效率不高，遇上大数据量通讯弊端明显。

介绍

本文将使用TSAL6200发射头和HS0038接收头传递信号。HS0038会输出解码完成的信号并以高低电频方式输出。